XTS-4802G：48N + 2G Ethernet Switch Controller
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产品名称:
XTS-4802G：48N + 2G Ethernet Switch Controller
产品型号:
XTS-4802G：
产品展商:
深圳市卓杰电子有限公司
简单介绍
48N + 2G Ethernet Switch Controller
XTS-4802G：48N + 2G Ethernet Switch Controller的详细介绍
desc-ription:
xts-4802g is a high performance, wire speed layer 2 ethernet switch that supports 48 10/100 mbps ports for downstreams and 2 10/100/1000 mbps ports for upstreams in a single asic.for smart switch application, the combination of mib counters, port-based vlan, and external cpu for read / write of packets counter and nway registers supported by xts-4802g make it possible for user to disable / enable ports, disable / enable broadcast throttling, change speed and duplex mode and change vlan port mapping remotely.
xts-4802g supports hardware based nway, this enables it to make nway change much faster than software-based solutions and eliminates the need for software development.
xts-4802g is fully compliant with ieee802.3x for flow control in full duplex mode. flow control in half duplex mode is supported using backpressure algorithm. the amount of bandwidth consumed by broadcast on any given segment can be controlled by broadcast filtering to prevent abnormal broadcast activity from disrupting network performance.
xts-4802g has the lowest per port cost among the existing 48+2g solutions worldwide. because the amount of heat generated is low enough to be dissipated via heat sink, no forced cooling fan is required.
features:
＊ 48 10/100 mbps ports + 2 10/100/1000 mbps ports layer-2 ethernet switch with embedded look up table and packet buffer
＊ sssmii for 10/100 mbps ports
＊ mii, gmii, or tbi for gigabit ports:
1. complies with 802.3z and 802.3ab
2. full duplex for mii, gmii, and tbi
3. built-in pcs for serdes transceiver
＊ auto-negotiation for speed and duplex mode se-lection
＊ built-in 8k entries into the mac address look up table with auto-aging and auto-learning capabilities
＊ built-in 3.7 mbits ssram with 0.5 mbits for mac address loop up table and 3.2 mbits for packet buffer
＊ store and forward architecture and head-of-line blocking prevention
＊ 802.3x full duplex flow control and backpressure half duplex flow control
＊ phy register read / write access
＊ 8051 cpu interface
＊ led interface for gigabit ports (rx active / tx active / link status)
＊ 0.18 m, 1.8v core with 3.3v i/o
＊ 272-pin pbga package
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